Various video coding standards have been developed to reduce the required bitrate for video transmission or the required capacity for storage. For example, MPEG-2, MPEG-4 and AVC/H.264 have been widely used in various applications. In recent years, the coding efficiency has been substantially improved in newer video compression formats such as VP8, VP9 and the emerging HEVC (High Efficiency Video Coding) standards.
In various devices that involve image display, there is another type of application that requires data compression. In particular, display links connecting computers to monitors, set-top boxes to televisions, and application processors to display panels are digital interface formats widely used in the industry. Display links use digital interfaces. With the increasing demand for higher display resolutions and higher frame rates, the amount of data sent over display links becomes extremely high. For example, the display link between a set-box device and a 1080p HDTV at 120 Hz frame rate will require more than 7 Gbits/sec. For UHD (Ultra High Definition) TV, the required data will be four-fold higher. Therefore, display links are often in compressed formats. For example, DSC (Display Stream Compression) standard has been developed jointly by VESA (Video Electronics Standards Association) and MIPI Alliance to address the needs for data compression in display applications.
Due to different requirements, the DSC standard is different from popular video coding standards, such as MPEG-2/4, AVC/H.264 and HEVC. For example, the color space used for compression in display applications may be the YCoCg color space, instead of the YUV color space. Furthermore, DSC only includes Intra-frame compression without Inter-frame compression to minimize the processing delay and avoid the need for reference picture buffer. In typical applications, the compression ratios required for DSC is much smaller than those for video storage or network delivery. FIG. 1A illustrates major functional blocks of an exemplary DSC encoder. As shown in FIG. 1A, the DSC encoder includes a source buffer 110, a predictor/quantization/reconstruction unit 112, a VLC entropy coding unit 114, a flatness determination unit 116, a rate control unit 118, a line buffer 120, and an indexed color history (ICH) unit 122. If the input image data are in the RGB color format, a color-space converter (not shown in FIG. 1A) corresponding to a RGB-to-YCoCg color format converter is utilized in the DSC encoder. The information from the flatness determination unit 116 can be used to adjust the QP (quantization parameter) in the rate control unit 118. As shown in FIG. 1A, the flatness indication is entropy coded using the VLC entropy coding unit 114 and incorporated in the bitstream. According to DSC, the pixels are processed using a 1×3 block size as shown on FIG. 1B, where a current block 130 is predicted by a reference block 132 in the same pixel row. The location of the reference block 132 is indicated by a corresponding block vector 134.
Upon the growing needs for display links to support higher display resolutions and higher bit depth for color components, VESA initiated development efforts to establish a standard for Advanced Display Stream Compression (ADSC). Also, the ADSC supports native 4:2:0 and 4:2:2 coding to eliminate the need for converting pixels into RGB components. For example, ADSC allows more efficient compression in YCbCr 4:2:0 color sampling format. In addition, ADSC also supports High Dynamic Range (HDR) to accommodate the higher color depth in newer TV shows and movies.
The processing for display links often uses block-based compression, where a picture is divided into blocks and the compression is applied to each block. Furthermore, the compression settings may be applied to an image unit smaller than a picture. For example, Advanced DSC (ADSC) being developed is applied to slices of each picture and the target bitrate is imposed on each slice. Each slice is divided into coding units (i.e., blocks) and each coding unit consists of a block of N×M pixels, where N corresponds to block height and M corresponds to block width. According to ADSC, the characteristics of each block are evaluated in terms of “flatness”, where the flatness of each block is categorized into five flatness types as follows:                Type: −1 denotes the “complex block”        Type: 0 denotes the “flat region”        Type: 1 denotes the “flat region (less flat than type 1)”        Type: 2 denotes the “complex to flat block”        Type: 3 denotes the “flat to complex block”        
The flatness type is determined according to the complexity information of each block and its neighboring blocks. Flatness type influences the rate control behavior in each block. According to the existing ADSC draft standard, the syntax of flatness type is signaled in each coding unit.
It is desirable to further improve the compression efficiency of the ADSC. In particular, the present invention addresses performance improvement for the block prediction mode.